This invention relates to a semiconductor devices, for example, high performance transistors, and architectures, and techniques for fabricating such devices and architectures; and more particularly, in one aspect, to a semiconductor device including a memory section (for example, transistors are dynamic random access memory cells (“DRAM”) wherein such cells have an electrically floating body in which an electrical charge is stored) and a logic section (including, for example, high performance transistors and non-high performance transistors) fabricated and/or disposed on the same substrate (for example, the same semiconductor die).
There is a continuing trend to fabricate advanced integrated circuits using techniques, materials and devices that improve performance, reduce leakage current and enhance overall scaling. Silicon-on-Insulator (SOI) is a material in which such devices may be fabricated on or in (hereinafter collectively “on”). Such devices are known as SOI devices and include, for example, partially depleted (PD), fully depleted (FD) devices, multiple gate devices (for example, double or triple gate), fin-shaped field effect transistor (“Fin-FET”), or gate all around devices. SOI devices have demonstrated improved performance (for example, speed), reduced leakage current characteristics and considerable enhancement in scaling.
With reference to FIGS. 1A-1C, three dimensional and cross-sectional views of Fin-FET or multiple gate SOI transistor 10 tend to appear quite similar. Moreover, the fabrication and configuration of multiple gate SOI transistor 10 typically involves first defining (using conventional lithographic and etching techniques) an upper or top layer of silicon of SOI wafer 12 (typically having a thickness of 10 to 200 nm) to define segments or pieces 14 that constitute the active regions of transistor 10 (i.e., source 16, drain 18, and body 20). Thereafter, dielectric material is deposited or formed (for example, via oxidation) on silicon segments 12 to form gate dielectric 22. A gate material (for example, a highly conductive silicon-based material) is then deposited and patterned to form gate 24 of transistor 10 which, as illustrated in FIG. 1A, is disposed on, juxtaposed and/or “covers” a plurality of interfaces (in the illustrative embodiment, three) of silicon segments or pieces 14 of SOI transistor 10.
Notably, the cross sectional view of FIG. 1B is taken through the gate region and along the longitudinal axis of the gate region of FIG. 1A (along lines B-B′) and, as such, the source and drain regions are not illustrated because they are in a direction perpendicular to that axis. Moreover, the cross-sectional view of FIG. 1C is taken through the source and drain regions and perpendicular to the longitudinal axis of the gate (along lines C-C′).
An advantage of such structures is performance (for example, speed) because, in operation, a channel forms in the body adjacent or beneath each of the gate-body interfaces. In the illustrative embodiment of FIG. 1A, three channels may form: two channels may be vertical and one channel may be horizontal. As such, the overall current drive of SOI transistor 10 is higher thereby facilitating higher performance or speed.
Another aspect of such transistors is that certain characteristics of the transistor may be determined by selecting the width of the silicon segments or pieces 14. In this regard, the width of the silicon segments or pieces 14 may be selected or designed so that during operation the full body of transistor 10 is fully depleted or controlled completely by the voltage applied to gate 24.
Such transistors may be well suited for microprocessors, microcontrollers or the like (hereinafter collectively “microprocessors”). In the context of microprocessors, currently less than half of the die of a microprocessor is occupied by or contains advanced logic transistors. Memory cells (and peripheral circuitry) reside on the remaining area of the die.
With reference to FIGS. 2A-2C, memory cell 26 proposed for SOI materials may be based on, among other things, a floating body effect of SOI transistors. (See, for example, U.S. patent application Ser. No. 10/450,238, Fazan et al., filed Jun. 10, 2003 and entitled “Semiconductor Device” (hereinafter “Semiconductor Memory Device Patent Application”; the contents of which are incorporated by reference herein). In this regard, memory cell 26 may consist of a PD or a FD SOI transistor 28 having a channel (between source region 30 and drain region 32), which is disposed adjacent to body region 34 and separated therefrom by gate dielectric. The body region 34 is electrically floating. A gate 36 is employed (in conjunction with source region 30 and drain region 32, among other things) to control the operation of memory cell 26.
With reference to FIGS. 3A, 3B, 4A and 4B, in one embodiment, data is written into or read from a selected memory cell 26 by applying suitable control signals to a selected word line(s) 40, a selected source line(s) 42 and/or a selected bit line(s) 44. In response, majority charge carriers 46 are accumulated in or emitted and/or ejected from electrically floating body region 34 wherein the data states are defined by the amount of carriers within electrically floating body region 34. In one embodiment, memory cell 26 operates by accumulating in or emitting/ejecting majority carriers (electrons or holes) 46 from body region 34 of, for example, N-channel transistors. (See, FIGS. 4A and 4B). In this regard, accumulating majority carriers (in this example, “holes”) 46 in body region 34 of transistors 28 via, for example, impact ionization near source region 30 and/or drain region 32, is representative of a logic high or “1” data state. (See, FIG. 4A). Emitting or ejecting majority carriers 46 from body region 34 via, for example, forward biasing the source/body junction and/or the drain/body junction, is representative of a logic low data state (“0”). (See, FIG. 4B).
Such memory cells, in addition to having low leakage current characteristics, facilitate implementing high-density memory cell arrays. While it may be advantageous to integrate SOI logic transistors and SOI memory cells on a single die to, among other things, reduce the overall dimensions of the die, fabricating an integrated device having SOI logic transistors and SOI memory cells may be challenging because each have unique and/or differing fabrication considerations. There is a need for a method of fabricating an integrated circuit device comprised of high performance SOI transistors (for example, Fin-FET and multiple gate structures) and SOI memory cells (for example, PD or FD SOI memory cells). Indeed, there is a need for a high performance integrated circuit device having SOI logic (including high performance and/or non-high performance transistors) and SOI memory that each include improved performance (for example, speed), reduced leakage current characteristics and/or considerable enhancement in scaling and density.